In the production of relatively simple integrated circuit devices, such as RAM chips or simple logic arrays, quality control during testing is achieved by discarding chips that fail post-fabrication testing. Very complex integrated circuit devices, such as high-order controllers, systems-on-a-chip (SOC), and other devices, however, can be too expensive to throw away.
Furthermore, as complex devices get faster and their characteristic feature sizes get smaller, the probability of the occurrence of errors increases, even in the most rigorous of manufacturing environments. Thus testing becomes an ever more important consideration in the progression of design to device to product.
Built-in Self Test (BIST) is the technique of designing additional hardware and software features into integrated circuits to allow them to perform self-testing. Built-in self-testing means that integrated circuits can test their operation using their own circuits, reducing their dependence on expensive external automated test equipment (ATE). Built-in-self-testing can work closely with built-in-repair-analysis (BIRA), which can, in many instances, repair parts of integrated circuits that fail built-in-self-test, often by readdressing portions of an element to substitute a redundant element for one that fails testing.
Built-in Self Test is also commonly used for testing of circuits that have no direct connections to external pins, such as embedded memories used internally by various devices. Embedded memories are particularly amenable to testing and repair regimens because of the repetitive nature of rows and columns of memory cell arrays. Embedded static Ram (SRAM) devices require especially rigorous testing, often not exhibiting errors unless fully stressed at speeds commensurate with normal operation.
It is noted also that modern embedded memory can contain many millions of memory cells and the loss of any memory cell can be detrimental to the operation of the integrated circuit. Furthermore, the manufacture of complex integrated circuit devices is expensive and time consuming. With millions of memory cells, there is a likelihood that one or more memory cells will fail testing. Instead of replacing an entire integrated circuit, it is often more expedient to build in a means of repairing memory.
With the increasing complexity of highly integrated circuit chips and the need to provide more rigorous testing logic, the chip space, or real estate, devoted to built-in-self-test and built-in-repair-analysis logic sections becomes large and costly. In devices which have relatively large embedded memories designed into the chip, the testing and repair logic can take up large amounts of chip area real estate.
What is needed, then, is a built-in means of testing embedded memory under high-stress conditions, identifying faulty memory cells, and repairing such memory. Such means should be designed into the integrated circuit and not take up too much “real estate”, or surface area.